The present invention relates to phase locked loops (PLL) and, more particularly, to means for reducing the current during fast lock up conditions when the PLL is out of the lock up range of the voltage controlled oscillator (VCO) of the PLL.
In a PLL system it is often desirable to speed up the lock up time for acquiring an input signal. One of the most common methods of providing fast lock up is to increase the loop filter charging current when the PLL is out of lock. However, if the input signal is out of the lock up range of the VCO, the phase detector of some, if not all, prior art PLL's will pull the control voltage all the way to one end of its range and the high charging current will continue to charge the loop filter at the beat note frequency (the frequency difference between the input signal and the VCO output). In battery operated equipment this represents unwanted current drain, and in radio receivers the pulsating current may couple into the audio circuits through common impedances which is undesirable.
Hence, a need exists for a means for reducing the fast lock current drain whenever the PLL is at either end of the lock up range.